1. Field of the Invention
This invention relates to a method of fabricating an isolation structure of integrated circuit (IC), and more particularly, to a method of fabricating a shallow trench isolation (STI) structure to avoid dislocation.
2. Description of Related Art
An intact IC is formed of thousands or millions of metal oxide semiconductor (MOS) transistors. For example, a dynamic random access memory (DRAM) or a static random access memory (SRAM) is one of this intensive type of semiconductor circuit. As the integration of the devices becomes higher and higher, the isolation between the devices becomes more important than before. To prevent short circuit occurring at adjacent transistors, a dielectric layer used for isolation is usually added for enhancing the insulation effect. The dielectric layer is so called field oxide (FOX). The conventional local oxidation technique (LOCOS) has the disadvantages of stress, the formation of bird's beak so that it is now less used. More recently, the field oxide layer now is mostly formed by shallow trench isolation technique.
Typically, the STI is formed by the following steps. After the formation of the shallow trenches, a liner oxide layer is formed on the inner surface of the shallow trench. The material of the liner oxide layer is usually silicon dioxide. The trenches are then fully filled with silicon dioxide. The silicon dioxide in the trenches is then densified at high temperature. However, during the process of densification, as the stress is higher than the critical point, dislocation may occur to reduce the strain energy caused by the stress, which is undesired.
The formation of the STI structure is strongly effected by the layout. The silicon dioxide grows along the orientation of (111) at the trench corner. Therefore, at the trench corner, the growth rate of the silicon dioxide is slower than at the trench sidewall. Consequently, the silicon dioxide layer at the trench corner is thinner. Moreover, silicon oxide produces compress stress on the substrate so that the phenomenon of dislocation may occur below the active region and the are a adjacent the STI and also below the STI region. Especially, for the product like SRAM, dislocation tends to occur along the low energy orientation (111). Dislocation is one of the main reasons of leakage current.
FIG. 1A to FIG. 1D are cross sectional views showing a conventional process of forming a shallow trench isolation structure.
Referring to FIG. 1A, on a substrate 100, a pad oxide layer is formed by thermal oxidation. A silicon nitride layer is then deposited by chemical vapor deposition (CVD). Then, after a photoresist layer 106 is primed, the wafer is processed through photolithography to define the STI region. An anisotropic dry etching, using plasma, is the used to form a pad oxide layer 102 and a silicon nitride layer 104. As the anisotropic dry etching process continues, a shallow trench 107 down to the substrate 100 can be formed.
Referring to FIG. 1B, after removing the remained photoresist layer 106, a thermal oxidation process is performed to form a liner oxide layer 112 on the exposed surface of the shallow trench 107. However, at the top corner 111 and the bottom corner 113, the silicon oxide layer grows slower and therefore the thickness is thinner. On the other hand, at the middle part of the periphery of the shallow trench 107, silicon oxide grows faster and therefore the thickness at this region is thicker. Consequently, the liner oxide layer 112 is thicker at the middle part of the periphery but thinner at the top corner and the bottom corner.
Referring to FIG. 1C, silicon oxide 122 is deposited into the shallow trench 107 so that the level of the silicon oxide layer 122 is higher than the silicon nitride layer 104 by using atmospheric pressure chemical vapor deposition (APCVD). Next, the silicon oxide layer 122 is densified. Usually, the process of densification is performed at about 1000.degree. C. Due to the inconsistent thickness of the liner oxide layer 112, the compressive stress of the silicon oxide layer onto the substrate 100 would not be equal at different points so that dislocation occurs at the top corner and the bottom corner below the active region and below the STI region.
Referring to FIG. 1D, in the existence of slurry, a chemical mechanical polishing (CMP) is performed on the oxide layer 122 on the Wafer surface under a well-controlled pressure. The surface of the oxide layer 122 is polished until the surface of the silicon nitride layer 104 is exposed. Then, hot phosphoric acid is used to remove the silicon nitride layer 104 and hydrofluoric acid is used to remove the pad oxide layer 102 and the remained oxide layer 122 higher than the surface of the substrate 100 so that the oxide layer 122a is left in the shallow trench. By now, the STI isolation structure is completed; however, the phenomenon of dislocation occurs at the substrate 100.